In the manufacture of a semiconductor device, the wires for the chip in the “back end of the line” (BEOL) are usually formed by the so-called cloisonné process. In this process, the metal is uniformly deposited on the wafer, patterned with a mask, and then etched with a plasma reactive ion etch (RIE) tool to leave the metal isolated in regions where one desires the wires. Then the dielectric material is deposited, and polished using chemical mechanical planarization (CMP) to leave the conductors properly separated. One of the benefits of this process of forming the wires is that since the plasma RIE removes material on a “line of sight”, it is effective in removing the metal that might be deposited in topography that originated from a process operation at a prior level.
However, to both reduce costs and to utilize different, lower resistance materials for the construction of the metal wires, the cloisonné process is being replaced by the damascene process to form the wires in the BEOL. In this reverse process, the dielectric is first uniformly deposited, patterned with a mask and etched. Then the metal conductor is uniformly deposited such that it forms a conformal film over the entire wafer and fills the patterns that have been etched into the dielectric. Then, using CMP, the excess surface metal is removed to leave the wires filled with metal. One of the problems with this process is that since the metal is removed via CMP, which planarizes as it removes the excess material, residual metal can remain in topography that has been created at prior levels. That is, if there is a scratch or erosion in the dielectric, the metal will fill that void and cannot be removed easily via CMP without considerable overpolish and the resulting damage that it introduces.
A specific example of where this change in methodology of creating the wiring is necessary is the manufacture of semiconductor devices with copper BEOL wiring. Since there is no viable RIE process for etching copper currently available, it is the preferred technique to form the lines with the damascene process. In such a case, the local wiring of the semiconductor devices (that is at the lowest levels of the chip) usually utilizes tungsten as the conductor, which is then connected to the more global wiring in the BEOL which is made of copper. In this specific example, it is found that erosion or scratching of the oxide dielectric at the last tungsten level replicates up into the ensuing copper levels. The areas of erosion then lead to “puddles” of residual copper and the scratches leave “stringers” of the copper, each of which if not removed at the copper CMP step, would cause short-circuits. If these puddles or stringers are removed during the copper CMP step, it adds considerable processing time for the “overpolish”.
Since the removal of all of the surface metal is essential to eliminate these short circuits, and because the damascene process is sensitive to both the material and underlying topography of those materials, it is clear that the surface of the wafer must be highly planar (i.e. no existing topography) prior to the deposition of the metal. The obvious method of achieving this planarity is to polish the dielectric into which the metal will be inlaid to create a smooth, scratch-free film prior to metal deposition. However, this has the disadvantage that it would necessitate additional process steps (polishing and cleaning) and would result in a highly variable dielectric, and hence, conductor thickness. This would cause the undesirable result of having a variable resistance for the circuit.